Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2552052
date_generatedThu Jul 18 10:36:53 2019 os_platformWIN64
product_versionVivado v2019.1 (64-bit) project_idabb3df8c28b94fd7900618cd21b059b0
project_iteration1 random_id9dc3cfda37085491ab96defb8ae00c57
registration_id211309621_0_0_124 route_designTRUE
target_devicexc7s25 target_familyspartan7
target_packagecsga225 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD Athlon(tm) II X2 B24 Processor cpu_speed2992 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 basedialog_cancel=4 basedialog_close=1 basedialog_ok=106
basedialog_yes=3 basereporttab_rerun=1 clocknetworksreportview_clock_network_tree=4 closeplanner_cancel=1
closeplanner_yes=3 cmdmsgdialog_messages=6 cmdmsgdialog_ok=12 cmdmsgdialog_open_messages_view=1
cmdmsgtreedialog_cmd_msg_tree=6 cmdmsgtreedialog_ok=7 commandlinepanel_command=1 confirmsavetexteditsdialog_no=1
constraintschooserpanel_create_file=1 constraintschooserpanel_file_table=2 constraintsselectabletablepanel_view_clock_network=1 createconstraintsfilepanel_file_name=2
createsrcfiledialog_file_name=3 createsrcfiledialog_file_type=2 defaultoptionpane_close=1 definemodulesdialog_define_modules_and_specify_io_ports=4
editcreateclocktablepanel_edit_create_clock_table=7 editcreategeneratedclocktablepanel_edit_create_generated_clock_table=13 exploreaheadview_launch_selected_runs=1 expruntreepanel_exp_run_tree_table=6
filesetpanel_file_set_panel_tree=65 filesetpanel_messages=4 finder_add_new_criterion=1 flownavigatortreepanel_flow_navigator_tree=113
generatedclockcreationpanel_optional_multiply_frequency=1 generatedclocktablepanel_table=4 getobjectsdialog_find=9 getobjectspanel_append=1
getobjectspanel_set=2 hcodeeditor_blank_operations=3 hcodeeditor_commands_to_fold_text=2 hcodeeditor_diff_with=4
hduallist_find_results=3 hduallist_move_selected_items_to_right=2 hduallist_selected_names=2 hjfilechooserrecentlistpreview_recent_directories=1
hpopuptitle_close=1 languagetemplatesdialog_templates_tree=81 mainmenumgr_checkpoint=1 mainmenumgr_constraints=1
mainmenumgr_file=2 mainmenumgr_flow=2 mainmenumgr_ip=1 mainmenumgr_project=1
mainmenumgr_reports=2 mainmenumgr_run=4 mainmenumgr_tools=1 mainmenumgr_unselect_type=1
mainmenumgr_view=6 maintoolbarmgr_run=3 mainwinmenumgr_layout=2 msgtreepanel_message_severity=1
msgtreepanel_message_view_tree=19 msgview_information_messages=2 msgview_status_messages=2 navigabletimingreporttab_timing_report_navigation_tree=12
netlistschematicview_show_cells_in_this_schematic=1 netlistschematicview_show_io_ports_in_this_schematic=5 netlistschmenuandmouse_view=3 netlisttreeview_netlist_tree=32
pacommandnames_add_sources=8 pacommandnames_auto_update_hier=9 pacommandnames_fed_toggle_routing_resources=1 pacommandnames_goto_netlist_design=3
pacommandnames_run_bitgen=1 pacommandnames_run_implementation=1 pacommandnames_run_synthesis=2 pacommandnames_save_design=2
pacommandnames_schematic=2 pacommandnames_set_as_top=1 pacommandnames_show_connectivity=1 pacommandnames_show_hierarchy=1
pacommandnames_simulation_live_break=15 pacommandnames_simulation_live_restart=7 pacommandnames_simulation_live_run=121 pacommandnames_simulation_live_run_all=16
pacommandnames_simulation_relaunch=17 pacommandnames_simulation_run_behavioral=25 pacommandnames_zoom_fit=1 pacommandnames_zoom_out=3
paviews_code=4 paviews_device=16 paviews_hierarchy=1 paviews_project_summary=35
paviews_schematic=10 primaryclockspanel_recommended_constraints_table=4 progressdialog_background=1 projecttab_close_design=5
projecttab_reload=13 quickhelp_help=1 rdicommands_copy=6 rdicommands_delete=2
rdicommands_line_comment=1 rdicommands_save_file=41 rdiviews_waveform_viewer=31 rungadget_show_error_and_critical_warning_messages=1
rungadget_show_warning_and_error_messages_in_messages=3 saveprojectutils_save=11 saveschematicdialog_specify_output_pdf_file=1 schematicview_regenerate=1
schematicview_remove=4 schmenuandmouse_expand_cone=1 schmenuandmouse_save_as_pdf_file=1 sdcgetobjectspanel_specify_generated_clock_source_objects=9
sdcgetobjectspanel_specify_master_pin=5 selectmenu_highlight=1 selectmenu_mark=1 settingsprojectgeneralpage_target_language=1
signaltablepanel_signal_table=48 simulationliverunforcomp_specify_time_and_units=16 simulationobjectspanel_simulation_objects_tree_table=87 simulationscopespanel_simulate_scope_table=21
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=6 srcchooserpanel_create_file=3 srcmenu_ip_hierarchy=6 srcmenu_open_selected_source_files=1
srcmenu_refresh_hierarchy=1 stalemoreaction_out_of_date_details=1 stalerundialog_no=1 stalerundialog_open_design=1
stalerundialog_run_synthesis=1 statemonitor_reset_run=1 statemonitor_reset_step=1 syntheticagettingstartedview_recent_projects=4
syntheticastatemonitor_cancel=2 taskbanner_close=26 timingconstraintswizard_goto_constraints_summary_page=1 timingconstraintswizard_view_timing_constraints=1
waveformnametree_waveform_name_tree=15 waveformview_goto_cursor=2 waveformview_goto_time_0=3 waveformview_next_transition=4
waveformview_previous_transition=1 xdccategorytree_xdc_category_tree=2 xdceditorview_apply_all_changes_to_xdc_constraints=2 xdctableeditorspanel_create_new_timing_constraint=1
java_command_handlers
addsources=11 closeproject=1 editdelete=3 fedtoggleroutingresourcescmdhandler=1
reportclocknetworks=1 runbitgen=1 runimplementation=8 runnoiseanalysis=1
runschematic=20 runsynthesis=8 savedesign=2 settopnode=1
showconnectivity=1 showhierarchy=1 showview=23 simulationbreak=15
simulationrelaunch=16 simulationrestart=7 simulationrun=25 simulationrunall=15
simulationrunfortime=115 timingconstraintswizard=1 toolssettings=1 toolstemplates=4
viewtaskimplementation=4 viewtaskrtlanalysis=3 viewtasksynthesis=5 xdccreategeneratedclock=1
zoomfit=1 zoomout=3
other_data
guimode=5
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_2 currentsynthesisrun=synth_2
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=57 simulator_language=Mixed srcsetcount=5 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=1 carry4=6 fdre=24 gnd=1
ibuf=1 lut1=1 lut5=2 lut6=3
obuf=4 vcc=2
pre_unisim_transformation
bufg=1 carry4=6 fdre=24 gnd=1
ibuf=1 lut1=1 lut5=2 lut6=3
obuf=4 vcc=2

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=12 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=6 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=12 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=3 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=3 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=45 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=90 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=45 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=6
fdre_functional_category=Flop & Latch fdre_used=24 ibuf_functional_category=IO ibuf_used=1
lut1_functional_category=LUT lut1_used=1 lut5_functional_category=LUT lut5_used=2
lut6_functional_category=LUT lut6_used=3 obuf_functional_category=IO obuf_used=4
slice_logic
f7_muxes_available=7300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=3650 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=14600 lut_as_logic_fixed=0 lut_as_logic_used=6 lut_as_logic_util_percentage=0.04
lut_as_memory_available=5000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=29200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=24 register_as_flip_flop_util_percentage=0.08
register_as_latch_available=29200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=14600 slice_luts_fixed=0 slice_luts_used=6 slice_luts_util_percentage=0.04
slice_registers_available=29200 slice_registers_fixed=0 slice_registers_used=24 slice_registers_util_percentage=0.08
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=14600 lut_as_logic_fixed=0
lut_as_logic_used=6 lut_as_logic_util_percentage=0.04 lut_as_memory_available=5000 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0 register_driven_from_outside_the_slice_used=0 register_driven_from_within_the_slice_fixed=0 register_driven_from_within_the_slice_used=24
slice_available=3650 slice_fixed=0 slice_registers_available=29200 slice_registers_fixed=0
slice_registers_used=24 slice_registers_util_percentage=0.08 slice_used=10 slice_util_percentage=0.27
slicel_fixed=0 slicel_used=6 slicem_fixed=0 slicem_used=4
unique_control_sets_available=3650 unique_control_sets_fixed=3650 unique_control_sets_used=1 unique_control_sets_util_percentage=0.03
using_o5_and_o6_fixed=0.03 using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=6
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7s25csga225-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=topMain -verilog_define=default::[not_specified]
usage
elapsed=00:00:59s hls_ip=0 memory_gain=575.461MB memory_peak=992.266MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::